Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Our mission at Google System Infrastructure is to build the best Cloud in the world for Google services and for cloud customers, by solving real world business challenges of performance, cost and scale, utilizing unique hardware, software, and system solutions.
As a Senior Automatic Test Pattern Generation (ATPG) Engineer, you'll work closely with various teams within the design process from architecture and frontend design, verification, and backend engineers to deliver the confidence needed in the design of the chip. You will be responsible for achieving manufacturing quality goals (coverage, Defective Parts Per Million (DPPM), etc.), reducing test cost, increasing production quality, and enhancing yield. You will also participate in silicon debug of structural tests.
Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.
Responsibilities
Oversee methodology, flows development, and automation for DFT ATPG in the overall ASIC design flow including analysis, insertion, assimilation in physical design flow, SDC, GL-SDF simulations, etc.
Define and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality.
Work with external vendors involved in implementing and validating test vectors. Generate structural vectors, analyze and debug scan coverage, and validate the vectors on Gate Level Simulator.
Work closely with the Physical Design team for mutual flows development and optimization such as scan insertion, chain reordering, patterns generation, coverage, compression ratio, ATPG power aware, formality, SDC modes.
Work with Post Silicon Engineering groups globally to develop mutual DFT flows and debug DFT at Post Silicon over ATE/System.
Requirements: Minimum qualifications:
Bachelor's degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
Experience with fault modeling Stuck-at, Transition, Path Delay, SDD, IDDQ, and other advanced fault models.
Experience in SoC cycles including DFT Specifications, pre silicon development, silicon bringup, and silicon debug.
Experience with DFT/ATPG/Physical Design flows co-development and assimilation using TCL or Python.
Experience with RTL Design for coding of DFT related logic.
Preferred qualifications:
Experience with physical design flows (e.g., Synthesis, Place and Route tools (P&R), or Static Timing Analysis (STA)).
Experience with STA constraints development and analysis for DFT modes and SDF simulations.
Experience with Verilog/System Verilog RTL Coding and/or Verification.
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