Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission at Google System Infrastructure is to build the best cloud in the world for Google services and for Google Cloud customers, by solving world business challenges of performance, cost, and scale, utilizing unique hardware, software, and system solutions. To better serve the rapidly evolving cloud needs, Google is establishing a team in Israel to develop custom chips for servers.
In this role, you will perform formal verification of design properties of ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You will also help define and improve design and verification methodologies that allow you to achieve formal verification closure.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the formal verification strategy and create the properties and constraints for digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
Contribute improvements to methodologies to enhance formal verification results.
Architect and implement reusable formal verification components.
Requirements: Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
5 years of experience working on main interconnects, Direct Memory Access (DMA), controllers, and power management.
Experience capturing design specification in a temporal assertion language such as SystemVerilog Assertion (SVA) or Property Specification Language (PSL).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science.
Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV.
Understanding of formal verification algorithms.
Proficiency with scripting languages, such as Python.
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